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Semiconductor MSM6636
Semiconductor
MSM6636
SAE-J1850 Communication Protocol Conformity Transmission Controller for Automotive LAN
GENERAL DESCRIPTION
The MSM6636 is a transmission controller for automotive LAN based on data communication protocol SAE-J1850. This LSI can realize a data bus topology bus LAN system with a PWM bit encoding method (41.6 K bps). In addition to a protocol control circuit, MSM6636 has an enclosed quartz oscillation circuit, host CPU interface (clock synchronous serial / UART), a transmit/ receive buffer, and a bus receiver circuit that decreases the burden on the host CPU.
FEATURES
* Based on SAE-J1850 CLASS B DATA COMMUNICATION NETWORK INTERFACE (issued August 12, 1991) * CSMA/CD (Carrier-sense multiple access with collision detection) * Internal transmit buffer (1 frame) and receive buffer (2 frames) * Bit encoding: PWM (Pulse Width Modulation) * Transmission Speed: 41.6K bps * Multi-address setting with physical addressing: 1 type / functional addressing: 15 types * Address filter function by multi-addressing (broadcasting possible) * Automatic retransmission function by arbitration loss and non ACK * 3 types of in-frame response support: q Single-byte response from a single recipient w Multi-byte response from a single recipient (with CRC code) e Single-byte response from multiple recipients (ID response as ACK) * Error detection by cyclic redundancy check (CRC) * Various communication error detections * Dual-wire bus abnormality detection by internal bus receiver and fault tolerance function * Host CPU interface is LSB first / serial, 4 modes supported q Clock synchronous serial (no parity) Normal mode: 8-bit data MPC Mode: 8-bit data + MPC bit (1: address / 0: data select bit) w UART (yes/no parity selectable) Normal mode: 1 start bit + 8-bit data + (parity) + 1 stop bit MPC mode: 1 start bit + 8-bit data + MPC bit + (parity) + 1 stop bit * Sleep Function Low current consumption mode by oscillation stop (IDS Max < 50A) SLEEP / WAKE UP control from host CPU, WAKE UP via LAN bus * Available package 18pin DIP, 18 pin QFJ (PLCC) and 24pin SOP.
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MSM6636
Semiconductor
BLOCK DIAGRAM
Buffer Register Receive Register Serial Interface Receive Buffer S-P Converter CRC Checker
LAN Controller PWM Decoder Degital Filter Bus Receiver
LAN Bus Input
Address Register
Address Filter Receive Controller
CPU
Status Register
Transmission Register CRC Generator P-S Converter
Transmission Controller
Response Register x'tal Clock Generator
PWM Encoder
LAN Bus Output
MSM6636
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Semiconductor
MSM6636
PIN CONFIGURATION (TOP VIEW)
18pin Plastic DIP AVDD 1 BO- BI- BI+ BO+
2 3 4 5 18 17 16 15 14 13 12 11 10
18pin Plastic QFJ BO- AVDD DVDD RES DVDD RES INT TXD RXD SCLK /PAE A-D OSC0 M-N DGND OSC1 OSC0 OSC1
8 9 10 11
24pin Plastic SOP AVDD BO- BI- BI+ BO+ NC NC NC AGND U-C M-N DGND
1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
2
1
18 17 16 15 14 13 12
BI- BI+ BO+ AGND U-C
3 4 5 6 7
INT TXD RXD SCLK /PAE A-D
AGND 6 U-C M-N
7 8
DVDD RES INT TXD RXD NC NC NC SCLK/PAE A-D OSC0 OSC1
DGND 9
NC: No Connection
PIN DESCRIPTION
Pin # Pin Name AVDD BO - BI - BI + BO + AGND U-C M-N DGND OSC 1 OSC 0 A-D SCLK / PAE RXD TXD INT RES DVDD DIP/ QFJ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SOP 1 2 3 4 5 9 10 11 12 13 14 15 16 20 21 22 23 24 I/O -- O I I O -- I I -- O I I I I O O I -- Function Analog power supply pin LAN - BUS output - LAN - BUS input - LAN - BUS input + LAN - BUS output + Analog ground pin 0: UART 1: clock synchronous serial select pin 1:normal mode select pin 0: MPC mode Digital ground pin Crystal oscillation output Crystal oscillation input 0: data communication 1: address communication Serial clock input/Parity select pin Serial data input pin Serial data output pin Interrupt output pin Reset input pin Digital power supply pin
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MSM6636
Semiconductor
ABSOLUTE MAXIMUM RATINGS
DGND = AGND = 0V Parameter Power Supply Voltage Input Voltage Output Voltage Power Dissipation Storage Temperature Symbol DVDD, AVDD VI VO PD(DIP)*1 PD(QFJ)*2 PD(SOP)*3 TSTG AVDD = DVDD AVDD = DVDD Ta = 25C Ta = 25C Ta = 25C Condition Rated Value -0.3~7.0 -0.3~DVDD+0.3 -0.3~DVDD+0.3 860 960 830 -55~150 Unit V V V mW mW mW C
PD(DIP)*1: 18PIN DIP package power dissipation PD(QFJ)*2: 18PIN QFJ package power dissipation PD(SOP)*3: 24PIN SOP package power dissipation Power Dissipation Curve
< 18PIN DIP package > 1000 860 Power dissipation PD(QFJ) [mW] Power dissipation PD(DIP) [mW] 1000 960
< 18PIN QFJ package >
500
500
-40 25
125 150
-40 25
125 150
Ambient temperature Ta (C) < 24PIN SOP package >
Ambient temperature Ta (C)
Power dissipation PD(SOP) [mW]
1000 830 500
-40 25
125 150
Ambient temperature Ta (C)
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Semiconductor
MSM6636
OPERATION RANGE
DGND = AGND = 0V Parameter Power Supply Voltage Operating Frequency Operating Temperature Symbol DVDD, AVDD fOSC Ta Condition AVDD = DVDD DVDD = AVDD = 5V10% Rated Value 4.5~5.5 2~16 -40~+125 Unit V MHz C
ELECTRICAL CHARACTERISTICS
DC Characteristics
DVDD = AVDD = 5V10%, DGND = AGND = 0V, Ta = -40 ~ +125C Parameter H Level Input Voltage L Level Input Voltage H Level Input Voltage L Level Input Voltage Receiver Hysteresis Width H Level Input Current L Level Input Current H Level Input Current L Level Input Current H Level Input Current L Level Input Current H Level Output Voltage L Level Output Voltage H Level Output Voltage L Level Output Voltage GND Offset Voltage Current Consumption 1 Current Consumption 2 Symbol Condition Application VIH1 VIL1 VIH2 VIL2 VH IIH1 IIL1 IIH2 IIL2 IIH3 IIL3 VOH1 VOL1 VOH2 VOL2 VOFF IDS IDD -- -- -- -- -- VI = VDD VI = 0V VI = VDD VI = 0V VI = VDD VI = 0V IO = -400A IO = +3.2mA IO = -4.0mA IO = +4.0mA -- During sleep f = 16MHz, no load A A F F F B B C C BI (+) BI (-) D D E E -- -- -- MIN DVDD 0.8 DGND - 0.3 DVDD - 2.0 DGND - 1.0 100 -- -- -- -- -- -- DVDD - 0.4 -- DVDD - 0.4 -- -- -- -- TYP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MAX DVDD + 0.3 DVDD 0.2 DVDD + 1.0 DGND + 2.0 400 +1 -1 +1 - 100 + 100 - 100 -- DGND + 0.4 -- DGND + 0.4 1 50 10 Unit V V V V mV A A A A A A V V V V V A mA
A: RES, SCLK/PAE, RXD, U-C, M-N, A-D, OSC0 B: SCLK/PAE, RXD, U-C, M-N, A-D C: RES D: TXD, INT E: BO-, BO+ F: BI-, BI+
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MSM6636
Semiconductor
AC Chacteristics PWM Bit Timing
Transmit min 23.64 6.90 14.87 30.54 47.28 38.42 47.28 70.92 94.56 8.86 typ 24.00 7.00 15.00 31.00 48.00 39.00 48.00 72.00 96.00 9.00 max 24.36 7.11 15.23 31.47 48.72 39.59 48.72 -- -- 9.14 Receive min 21.00 5.00 13.00 29.00 45.00 37.00 43.00 69.00 86.00 4.00 max 28.00 12.00 20.00 36.00 52.00 44.00 51.00 76.00 -- 15.00
Parameter Bit Length "1" Dominant Width "0" Dominant Width "SOF" Dominant Width "SOF,BRK" Length "BRK" Dominant Width "EOD" + Bit Length "EOF" + Bit Length "EOF + IFS" + Bit Length "0" Passive Width
Symbol TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10
Unit s s s s s s s s s s
Note: DVDD = AVDD = 5 V 10%, Ta = -40 ~ +125C, In setting 41.6 K bps
Dominant "1" Passive Dominant "0 " Passive TP3 TP1 TP10 Dominant " SOF " Passive TP4 TP5 TP2
Dominant " EOD " Passive LAST BIT TP7 " EOF " " IFS " Dominant Passive LAST BIT TP8 TP9 Dominant " BRK " Passive TP6 TP5 EOF IFS EOD
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Semiconductor
MSM6636
CPU Serial Interface Timing mClock synchronous Serial
DVDD=AVDD=5V10%, Ta =-40~+125C Parameter OSCO (source oscillation) Pulse Cycle SCLK-L Interval Width SCLK-H Interval Width SCLK - RXD Setup Time SCLK - RXD Hold Time SCLK - TXD Output Delay Time A-D - SCLK Setup Time SCLK - A-D Hold Time SCLK Frame Interval Time *1 SCLK Frame Interval Time *2 Symbol to tCKLW tCKHW tSRS tSRH tSTD tAS tAH tINT1 tINT2 Min 62 8to 8to 4to 4to 4to 0 8to 8to 16to Typ -- -- -- -- -- -- -- -- -- -- Max 500 -- -- -- -- 6to + 100 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns
SCLK Frame Interval Time *1 Between "Communication type (WR) and address setting" frame and "WR data" frame. Between "WR data" frame and "WR data" frame during continuous WR. SCLK Frame Interval Time *2 Between "Communication type (RD) and address setting" frame and "RD data" frame. Between "RD data" frame and "RD data" frame during continuous RD.
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MSM6636
Semiconductor
mUART
DVDD=AVDD=5V10%, Ta =-40~+125C Parameter A-D - STOP bit Setup Time STOP bit O - A-D Hold Time START bit O - TXD Output Delay Time Write Frame Interval Time *3 Read Frame Interval Time *4 Symbol tUAS tUAH tUTD tINT3 tINT4 Min 0 0 48to 0 10to Typ -- -- -- -- -- Max -- -- 50to + 100 -- -- Unit ns ns ns ns ns
Write Frame Interval Time *3 Between "Communication type (WR) and address setting" frame and "WR data" frame. Between "WR data" frame and "WR data" frame during continuous WR. Read Frame Interval Time *4 Between "Communication type (RD) and address setting" frame and "RD data" frame.
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Semiconductor
MSM6636
Wakeup Input Signal
DVDD=AVDD=5V10%, Ta =-40~+125C Parameter LAN bus Passive AE Dominant Change Pulse Width RXD Terminal Input Pulse Width Bus Receiver Stable Time *5 Symbol tWD tWR tRS Min 7 300 1 Typ -- -- -- Max -- -- -- Unit s ns s
to OSC0 tUAS A-D RXD STOP tINT3 tINT4 START tUAH
TXD
tUTD
START
STOP bit Termination
Note: The time chart shows the wakeup input signals from each sleep status Bus Receiver Stable Time *5 The stable time of the bus receiver is from just after wakeup to the restart of message transmission and reception. However, the clock oscillation source should use an external clock. (A clock is input even in the sleep status.)
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MSM6636
Semiconductor
Fault Tolerant Function Operation Conditions
DVDD=AVDD=5V10%, Ta =-40~+125C, In setting 41.6Kbps Parameter LAN bus (+) VDD Short Circuit Detection Pulse Width LAN bus (-) GND Short Circuit Detection Pulse Width LAN bus (-) VDD Short Circuit Detection Pulse Width Symbol tPV tNG tNV Min 5 48 48 5 Typ -- -- -- -- Max -- -- -- -- Unit s s s s LAN bus (+) GND Short Circuit Detection Pulse Width tPG
BUS(+) BUS(-) tPG BUS(+) BUS(-) tNV tNG tPV
Reset Input Pulse Width
DVDD=AVDD=5V10%, Ta=-40~+125C Parameter Reset Input Pulse Width Symbol tRES Min 0.1 Typ -- Max -- Unit s
RES tRES
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Semiconductor
MSM6636
APPLICATION EXAMPLE
Host CPU and LAN bus Connection Example Host CPU and LAN bus connection example of MSM6636 is shown below.
Unit A Host CPU SOUT SIN INT CLKOUT OPEN MSM6636 DVDD AVDD RXD TXD BO (+) INT OSC0 BI (+) OSC1 SCLK / PAE BI (-) U-C M-N BO (-) A-D RES DGND AGND
ZD ZD
RES
Unit B
. . .
Bus + Bus -
The above connection example is when "UART, MPC and parity no mode" was used as the "host CPU interface, and when CLKOUT output of the host CPU" was used as the clock for MSM6636. Depending on the control target, an optimum host CPU (number of ports, A/D converter yes / no) can be selected, and an optimum system can be constructed.
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